Wednesday, February 5, 2014

The Farhan Minima RF Mixer

I have been wanting a simple Mixer Circuit for experiments in my electronics shop, and most recently for use with my Small Signal Amplifier (see previous post).

Alan - K6ZY at the last Puget Sound QRP (pQRP) meeting mentioned he was considering building a Homebrew Farhan VU2ESE Minima Transceiver project.  After looking at the schematic for the Mimina, it appears that the Mixer Circuit would work very nicely as an stand-alone mixer for my experimental use. Very good documentation of the mixer's operation is provided by Farhan. The mixer used in the Minima has been dubbed the “KISS Mixer” by Chris Trask in his paper.

Minima Mixer Circuit in LTSpice
(See file below)
To play with the idea of building an experimental mixer, I created a LTSpice simulation circuit to start my understanding of it operation.

So far I have not gleamed much information from the LTSpice simulation, but maybe I have something wrong with my circuit; bias, configuration, signal levels or expected output. Or, maybe LTSpice can not deal with mixed signals correctly, but  I will continue working with LTSpice to learn more.

In preparation for my experiment and use of the Mixer Circuit, I have started the initial design of a PCB using DipTrace. Keeping with my ever present Goal of building electronic projects as small as I can, this initial design is larger than I think the final design will be, as I have currently configured it to used larger components than necessary. I think I can find small SOT-23 J310 JFET packages and smaller transformer cores. But this is a start.

Mixer Layout in DipTrace
 I have configured the PCB as a single-sided circuit as it can be produced with simple Homebrew Toner Transfer Method. But perhaps, using double-sided will be best for reducing the over all size.

This mixer as a stand-alone device will be very useful in my electronics shop - Thanks Farhan.




UPDATE: Aug 7, 2014 07:46

Here is my "SpiceMixer01.asc" file that I have been playing with.



Version 4
SHEET 1 880 680
WIRE -224 -352 -704 -352
WIRE -160 -352 -224 -352
WIRE 144 -352 -80 -352
WIRE 256 -352 224 -352
WIRE 256 -336 256 -352
WIRE -224 -320 -224 -352
WIRE -704 -288 -704 -352
WIRE 304 -288 224 -288
WIRE 144 -272 144 -288
WIRE 256 -272 144 -272
WIRE -224 -224 -224 -240
WIRE 144 -224 48 -224
WIRE 256 -224 256 -272
WIRE 256 -224 224 -224
WIRE 464 -224 256 -224
WIRE 544 -224 528 -224
WIRE -704 -192 -704 -208
WIRE -576 -192 -704 -192
WIRE 48 -192 48 -224
WIRE 304 -192 304 -288
WIRE -704 -160 -704 -192
WIRE -224 -144 -352 -144
WIRE -352 -128 -352 -144
WIRE 0 -128 -32 -128
WIRE 400 -128 352 -128
WIRE 544 -128 544 -224
WIRE 608 -128 544 -128
WIRE 544 -96 544 -128
WIRE -352 -80 -352 -128
WIRE -224 -32 -224 -64
WIRE -144 -32 -224 -32
WIRE 48 -32 48 -96
WIRE 48 -32 -64 -32
WIRE 176 -32 48 -32
WIRE 304 -32 304 -96
WIRE 304 -32 176 -32
WIRE -224 0 -224 -32
WIRE -352 32 -352 0
WIRE 544 32 544 -16
WIRE 400 128 400 -128
WIRE 400 128 224 128
WIRE 144 144 144 128
WIRE 256 144 144 144
WIRE -32 192 -32 -128
WIRE 144 192 -32 192
WIRE 256 192 256 144
WIRE 256 192 224 192
WIRE 320 224 320 192
WIRE -224 256 -720 256
WIRE -176 256 -224 256
WIRE 144 256 -96 256
WIRE -224 288 -224 256
WIRE 224 304 224 256
WIRE -720 320 -720 256
WIRE -224 400 -224 368
WIRE -720 432 -720 400
WIRE -560 432 -720 432
WIRE -720 448 -720 432
FLAG 176 32 0
FLAG 224 304 0
FLAG -352 32 0
FLAG 256 -336 0
FLAG -224 -224 0
FLAG -224 400 0
FLAG -352 -128 Bias
FLAG -224 -352 SigIn
FLAG -224 256 LO
FLAG 608 -128 SigOut
FLAG 544 32 0
FLAG -704 -80 0
FLAG -720 528 0
FLAG -576 -192 SampleSig
FLAG -560 432 SampleLo
FLAG -224 80 0
FLAG 320 224 0
SYMBOL ind2 128 144 R270
WINDOW 0 40 34 VTop 2
WINDOW 3 65 78 VBottom 2
SYMATTR InstName L1
SYMATTR Value {Lo}
SYMATTR Type ind
SYMBOL ind2 128 208 R270
WINDOW 0 34 32 VTop 2
WINDOW 3 60 86 VBottom 2
SYMATTR InstName L2
SYMATTR Value {Lo}
SYMATTR Type ind
SYMBOL ind2 128 272 R270
WINDOW 0 35 38 VTop 2
WINDOW 3 63 77 VBottom 2
SYMATTR InstName L3
SYMATTR Value {Lo}
SYMATTR Type ind
SYMBOL ind2 128 -336 R270
WINDOW 0 38 38 VTop 2
WINDOW 3 63 78 VBottom 2
SYMATTR InstName L4
SYMATTR Value {Ls}
SYMATTR Type ind
SYMBOL ind2 128 -272 R270
WINDOW 0 34 29 VTop 2
WINDOW 3 60 76 VBottom 2
SYMATTR InstName L5
SYMATTR Value {Ls}
SYMATTR Type ind
SYMBOL ind2 128 -208 R270
WINDOW 0 32 38 VTop 2
WINDOW 3 61 80 VBottom 2
SYMATTR InstName L6
SYMATTR Value {Ls}
SYMATTR Type ind
SYMBOL njf 0 -192 R0
SYMATTR InstName J1
SYMBOL njf 352 -192 M0
SYMATTR InstName J2
SYMBOL cap 160 -32 R0
SYMATTR InstName C1
SYMATTR Value .1uF
SYMBOL voltage -352 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5V
SYMBOL voltage -224 -336 R0
WINDOW 3 24 44 Left 2
WINDOW 123 24 72 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value SINE(0 10uV 7Meg)
SYMATTR Value2 AC 1mV
SYMATTR InstName V2
SYMBOL voltage -224 272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 70mV 0 0 0 {PulseWidth} {Period})
SYMBOL res -176 -336 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -5 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL res -192 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -5 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 50
SYMBOL res 528 -112 R0
SYMATTR InstName R3
SYMATTR Value 50
SYMBOL res -720 -304 R0
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL res -720 -176 R0
SYMATTR InstName R5
SYMATTR Value 1K
SYMBOL res -736 304 R0
SYMATTR InstName R6
SYMATTR Value 10Meg
SYMBOL res -736 432 R0
SYMATTR InstName R7
SYMATTR Value 1K
SYMBOL res -160 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 4.7K
SYMBOL res -240 -16 R0
SYMATTR InstName R9
SYMATTR Value 8K
SYMBOL res -240 -160 R0
SYMATTR InstName R10
SYMATTR Value 2K
SYMBOL cap 464 -208 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
TEXT -512 -280 Left 2 !.tran 0 10uS 9uS
TEXT 392 -416 Left 2 !.param Ls = 10000nH\n.param Lo = 10000nH\nKo L1 L2 L3 1\nKs L4 L5 L6 1
TEXT -800 -408 Left 6 ;WA0UWH
TEXT -272 448 Left 2 !.param Freq = 27Meg\n.param Period =  1 / Freq\n.param PulseWidth = Period / 2 * 1.05




-- Home Page: https://WA0UWH.blogspot.com

4 comments:

  1. Hello Eldon
    Perhaps you forgot to ground the secundary input trafo center, between L1 and L2.
    I've made some simulation on Minima mixer too. I'd rather ground the fets source pins and adjust the gate level between L1 and L2. It works the same, but I feel better grounding the fets source.
    73
    Klaus
    PY2KLA

    ReplyDelete
  2. Klaus,

    Thanks for your Comment, Yes, I agree, I published the circuit before I found the mistake.

    73

    ReplyDelete
  3. Eldon
    Please,could you post your comments about the simulation?
    I've found some noise on fet's drain. I think it's coming from gate to drain capacitance and part of the signal pass to drain when gate voltage signal rise. This noise passes back through the trafo. So during receiving there is some transmition...
    Do you have the same result?
    73
    Klaus
    PY2KLA

    ReplyDelete
  4. One more comment: at Minima, the RF BFO signal came from Si570 and it has a square wave shape. Maybe it is a good idea to change the V3 in your simulation from sine to square wave.
    I think the idea is to use the fets on close-open state, and less at linear condition.
    73
    Klaus
    PY2KLA

    ReplyDelete